788 search results - page 35 / 158 » Symbolic Equivalence Checking |
ESORICS
2007
Springer
14 years 3 months ago
2007
Springer
Abstract. We define a framework to reason about implementations of equational theories in the presence of an adaptive adversary. We particularly focus on soundess of static equiva...
FMCAD
2007
Springer
14 years 22 days ago
2007
Springer
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
CAV
2009
Springer
14 years 9 months ago
2009
Springer
Abstract. We present a new technique called Monotonic Partial Order Reduction (MPOR) that effectively combines dynamic partial order reduction with symbolic state space exploration...
BCS
2008
13 years 10 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
FMCAD
2006
Springer
14 years 15 days ago
2006
Springer
In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent yea...