243 search results - page 28 / 49 » Synchronous Elastic Circuits |
CHARME
1995
Springer
14 years 6 days ago
1995
Springer
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
TCAD
2002
13 years 8 months ago
2002
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
CHES
2004
Springer
14 years 2 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
ICCAD
1995
IEEE
14 years 5 days ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...