This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...
Among related synchronous programming principles, the model of computation of the Polychrony workbench stands out by its capability to give high-level description of systems where...
Jean-Pierre Talpin, Christian Brunette, Thierry Ga...
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
Evolving software-intensive systems from one consistent state to another is a challenging activity due to the intricate inter-dependencies among the components. In this paper, we ...
We propose a framework for the formal speci cation and veri cation of timed and hybrid systems. For timed systems we propose a speci cation language that refers to time only throug...