2 search results - page 1 / 1 » Synthesis and Floorplanning for Large Hierarchical FPGAs |
FPGA
1997
ACM
14 years 1 months ago
1997
ACM
CODES
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...