- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
This paper addresses the synthesis approach to output feedback robust model predictive control for systems with polytopic description, bounded state disturbance and measurement no...
BaoCang Ding, YuGeng Xi, Marcin T. Cychowski, Thom...
Time-driven simulation models typically model timing in an idealized way that is over-constrained and cannot be directly implemented. In this paper we present a transformation to ...
Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Erns...
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...