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ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
14 years 26 days ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
ICCAD
2005
IEEE
128views Hardware» more  ICCAD 2005»
14 years 4 months ago
Reducing structural bias in technology mapping
Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we ...
Satrajit Chatterjee, Alan Mishchenko, Robert K. Br...
CAL
2006
13 years 7 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
ICTAI
2002
IEEE
14 years 16 days ago
Distributed Graphplan
(Appears as a regular paper in the Proceedings of IEEE International Conference on Tools with Artificial Intelligence (ICTAI), Washington D.C, IEEE Computer Society, Nov. 2002, p...
Mark Iwen, Amol Dattatraya Mali
ISCAS
2005
IEEE
122views Hardware» more  ISCAS 2005»
14 years 1 months ago
A mixed analog-digital hybrid for speech enhancement purposes
Abstract— This paper presents and evaluates a hybrid implementation of a low complexity algorithm for speech enhancement, the Adaptive Gain Equalizer (AGE). The AGE is a subband ...
Benny Sallberg, Mattias Dahl, Henrik Akesson, Ingv...