5 search results - page 1 / 1 » Synthesis of asynchronous circuits for stuck-at and robust p... |
VLSID
1995
IEEE
14 years 9 months ago
1995
IEEE
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
ATS
2003
IEEE
14 years 11 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
ICCAD
1997
IEEE
14 years 10 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
ICCAD
2006
IEEE
15 years 2 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
VLSI
2005
Springer
14 years 11 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...