419 search results - page 23 / 84 » Synthesis of networks on chips for 3D systems on chips |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
ICETET
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
CAL
2008
13 years 8 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
FPL
2003
Springer
14 years 1 months ago
2003
Springer
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
RECONFIG
2009
IEEE
14 years 3 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...