419 search results - page 25 / 84 » Synthesis of networks on chips for 3D systems on chips |
ASAP
2003
IEEE
14 years 2 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
JSA
2008
13 years 8 months ago
2008
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
—In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource ...
ITCC
2005
IEEE
14 years 2 months ago
2005
IEEE
The interconnection network plays an important role in the performance and energy consumption of a Networkon-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based int...
RTSS
2008
IEEE
14 years 3 months ago
2008
IEEE
—Wormhole switching with fixed priority preemption has been proposed as a possible solution for real-time on-chip communication. However, none of current priority assignment pol...