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» Synthesis of networks on chips for 3D systems on chips
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 2 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
SAMOS
2005
Springer
14 years 2 months ago
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hie...
Erno Salminen, Tero Kangas, Jouni Riihimäki, ...
AINA
2009
IEEE
14 years 1 months ago
Differences and Commonalities of Service-Oriented Device Architectures, Wireless Sensor Networks and Networks-on-Chip
Device centric Service-oriented Architectures have shown to be applicable in the automation industry for interconnecting manufacturing devices and enterprise systems, thus, establ...
Guido Moritz, Claas Cornelius, Frank Golatowski, D...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 9 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...