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» Synthesizable High Level Hardware Descriptions
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DATE
2006
IEEE
141views Hardware» more  DATE 2006»
14 years 5 months ago
Evaluating coverage of error detection logic for soft errors using formal methods
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
Udo Krautz, Matthias Pflanz, Christian Jacobi 0002...
DAC
2008
ACM
14 years 12 months ago
Formal datapath representation and manipulation for implementing DSP transforms
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
Franz Franchetti, James C. Hoe, Markus Püsche...
FPL
2009
Springer
132views Hardware» more  FPL 2009»
14 years 2 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
14 years 2 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress
ET
1998
99views more  ET 1998»
13 years 10 months ago
A Behavior Model for Next Generation Test Systems
Defining information required by automatic test systems frequently involves a description of system behavior. To facilitate capturing the required behavior information in the cont...
Lee A. Shombert, John W. Sheppard