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» Synthetic Trace-Driven Simulation of Cache Memory
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AINA
2007
IEEE
14 years 5 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
14 years 2 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ICS
2001
Tsinghua U.
14 years 3 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
SIGMETRICS
1998
ACM
14 years 3 months ago
Modeling Set Associative Caches Behavior for Irregular Computations
While much work has been devoted to the study of cache behavior during the execution of codes with regular access patterns, little attention has been paid to irregular codes. An i...
Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapat...
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
14 years 3 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm