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DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 3 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
IPPS
1999
IEEE
14 years 1 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
ISWC
1998
IEEE
14 years 1 months ago
Development of a Commercially Successful Wearable Data Collection System
Symbol Technologies has completed a unique accomplishment; it has created a commercially successful Wearable Computer. The success of this product is directly due to a structured ...
Robert Stein, Stephen Ferrero, Margaret Hetfield, ...
TC
2010
13 years 7 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
TRIDENTCOM
2006
IEEE
14 years 3 months ago
Creating wireless multi-hop topologies on space-constrained indoor testbeds through noise injection
— To evaluate routing protocols on a controlled indoor wireless testbed, the radio range must be compressed so that larger multi-hop topologies can be mapped into a laboratorysiz...
Sanjit Krishnan Kaul, Marco Gruteser, Ivan Seskar