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VLSID
1999
IEEE
101views VLSI» more  VLSID 1999»
14 years 1 months ago
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
Ingo Sander, Axel Jantsch
IEEEPACT
2002
IEEE
14 years 1 months ago
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasu...
IISWC
2009
IEEE
14 years 3 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
FDL
2003
IEEE
14 years 2 months ago
Dynamic Power Management of an AMBA-based Platform in SystemC
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...
Massimo Conti, Marco Caldari, Simone Orcioni
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 6 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer