12333 search results - page 2301 / 2467 » System Level Modelling for Hardware Software Systems |
143
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IEEEPACT
2006
IEEE
15 years 8 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
114
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SENSYS
2004
ACM
15 years 7 months ago
2004
ACM
Developing sensor network applications demands a new set of tools to aid programmers. A number of simulation environments have been developed that provide varying degrees of scala...
150
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IWMM
2011
Springer
14 years 5 months ago
2011
Springer
We propose a new memory model called short-term memory for managing objects on the heap. In contrast to the traditional persistent memory model for heap management, objects in sho...
172
Voted
CAV
1998
Springer
15 years 6 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
133
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CCGRID
2009
IEEE
15 years 9 months ago
2009
IEEE
As high-end computing systems continue to grow in scale, the performance that applications can achieve on such large scale systems depends heavily on their ability to avoid explic...