Sciweavers

12333 search results - page 2301 / 2467
» System Level Modelling for Hardware Software Systems
Sort
View
IEEEPACT
2006
IEEE
14 years 2 months ago
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...
SENSYS
2004
ACM
14 years 1 months ago
Simulating the power consumption of large-scale sensor network applications
Developing sensor network applications demands a new set of tools to aid programmers. A number of simulation environments have been developed that provide varying degrees of scala...
Victor Shnayder, Mark Hempstead, Bor-rong Chen, Ge...
IWMM
2011
Springer
254views Hardware» more  IWMM 2011»
12 years 11 months ago
Short-term memory for self-collecting mutators
We propose a new memory model called short-term memory for managing objects on the heap. In contrast to the traditional persistent memory model for heap management, objects in sho...
Martin Aigner, Andreas Haas, Christoph M. Kirsch, ...
CAV
1998
Springer
175views Hardware» more  CAV 1998»
14 years 18 days ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
CCGRID
2009
IEEE
14 years 3 months ago
Natively Supporting True One-Sided Communication in
As high-end computing systems continue to grow in scale, the performance that applications can achieve on such large scale systems depends heavily on their ability to avoid explic...
Gopalakrishnan Santhanaraman, Pavan Balaji, K. Gop...
« Prev « First page 2301 / 2467 Last » Next »