169 search results - page 8 / 34 » System level memory optimization for hardware-software co-de... |
CONCURRENCY
2006
13 years 7 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications o...
JSA
2007
13 years 7 months ago
2007
Traditional design techniques for embedded systems apply transformations on the source code to optimize hardwarerelated cost factors. Unfortunately, such transformations cannot ad...
TPCTC
2010
Springer
13 years 2 months ago
2010
Springer
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Loop fusion and loop shifting are well recognized loop transformations for memory requirement reduction. Stateof-the-art optimizations with loop fusion and shifting are based on h...