82 search results - page 15 / 17 » SystemC transaction level models and RTL verification |
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, howe...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
DSD
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...