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CODES
2009
IEEE
14 years 21 days ago
Building heterogeneous reconfigurable systems with a hardware microkernel
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
Jason Agron, David L. Andrews
DELTA
2006
IEEE
14 years 13 days ago
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
Peter J. Green, Desmond P. Taylor
ASPLOS
2008
ACM
13 years 10 months ago
Optimistic parallelism benefits from data partitioning
Recent studies of irregular applications such as finite-element mesh generators and data-clustering codes have shown that these applications have a generalized data parallelism ar...
Milind Kulkarni, Keshav Pingali, Ganesh Ramanaraya...
CASES
2005
ACM
13 years 10 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
TIT
2010
111views Education» more  TIT 2010»
13 years 3 months ago
Directly lower bounding the information capacity for channels with I.I.D.deletions and duplications
We directly lower bound the information capacity for channels with i.i.d. deletions and duplications. Our approach differs from previous work in that we focus on the information ca...
Adam Kirsch, Eleni Drinea