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DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 22 days ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
NMR
2004
Springer
14 years 2 months ago
A resource bounded default logic
This paper presents statistical default logic, an expansion of classical (i.e., Reiter) default logic that allows us to model common inference patterns found in standard inferenti...
Gregory R. Wheeler
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
FOSSACS
1999
Springer
14 years 1 months ago
Probabilistic Temporal Logics via the Modal Mu-Calculus
This paper presents a mu-calculus-based modal logic for describing properties of reactive probabilistic labeled transition systems (RPLTSs) and develops a modelchecking algorithm ...
Murali Narasimha, Rance Cleaveland, S. Purushotham...
FSTTCS
2006
Springer
14 years 11 days ago
On Continuous Timed Automata with Input-Determined Guards
We consider a general class of timed automata parameterized by a set of "input-determined" operators, in a continuous time setting. We show that for any such set of opera...
Fabrice Chevalier, Deepak D'Souza, Pavithra Prabha...