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ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
15 years 8 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
MSS
1995
IEEE
148views Hardware» more  MSS 1995»
15 years 7 months ago
Client/Server data Serving for High-Performance Computing
This paper will attempt to examine the industry requirements for shared network data storage and sustained high speed (10’s to 100’s to thousands of megabytes per second) netw...
Chris Wood
121
Voted
ISCA
1991
IEEE
121views Hardware» more  ISCA 1991»
15 years 7 months ago
IXM2: A Parallel Associative Processor
This paper describes a parallel associative processor, IXM2, developed mainly for semantic network processing. IXM2 consists of 64 associative processors and 9 network processors,...
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, N...
SIGCOMM
2010
ACM
15 years 4 months ago
An open router virtualization framework using a programmable forwarding plane
Network virtualization promises to spur innovation and add flexibility to the Future Internet infrastructure. Routers supporting virtualization allow the deployment of concurrent ...
Zdravko Bozakov
153
Voted
ISCAS
2011
IEEE
237views Hardware» more  ISCAS 2011»
14 years 7 months ago
A new network-based algorithm for multi-camera abnormal activity detection
In this paper, a new abnormal activity detection algorithm is proposed for multi-camera surveillance applications. The proposed algorithm models the entire scene covered by the mu...
Hongyu Gao, Weiyao Lin, Xiaokang Yang, Hongxiang L...