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576views
17 years 5 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
LCPC
2004
Springer
15 years 11 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
ANSS
2004
IEEE
15 years 9 months ago
Cache Simulation Based on Runtime Instrumentation for OpenMP Applications
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
Jie Tao, Josef Weidendorfer
LCTRTS
2001
Springer
15 years 10 months ago
Middleware For Building Adaptive Systems Via Configuration
1 COTS (commercial off-the-shelf) devices are capable of executing powerful, distributed algorithms. Very large, adaptive systems can be created by simply integrating these devices...
Sanjai Narain, Ravichander Vaidyanathan, Stanley M...
TCAD
2008
114views more  TCAD 2008»
15 years 6 months ago
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...