1355 search results - page 3 / 271 » Techniques for Formal Verification of Digital Systems: A Sys... |
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
VLSID
1997
IEEE
13 years 12 months ago
1997
IEEE
CHARME
1997
Springer
13 years 11 months ago
1997
Springer
Formal verification techniques need to deal with the complexity of the systems rified. Most often, this problem is solved by taking an abstract model of the system and aiming at a...
FM
1999
Springer
13 years 12 months ago
1999
Springer
FORMATS
2009
Springer
13 years 11 months ago
2009
Springer
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...