66 search results - page 8 / 14 » Techniques for extracting instruction level parallelism on M... |
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
TPDS
2010
13 years 5 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
CF
2010
ACM
13 years 10 months ago
2010
ACM
: The SpiNNaker machine is a massively parallel computing system, consisting of 1,000,000 cores. From one perspective, it has a place in Flynns' taxonomy: it is a straightforw...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
HPCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...