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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 3 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
SOSP
2009
ACM
14 years 6 months ago
Fast byte-granularity software fault isolation
Bugs in kernel extensions remain one of the main causes of poor operating system reliability despite proposed techniques that isolate extensions in separate protection domains to ...
Miguel Castro, Manuel Costa, Jean-Philippe Martin,...
OOPSLA
2010
Springer
13 years 8 months ago
From OO to FPGA: fitting round objects into square hardware?
Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energyintensive operations in order to reduce overall energy consumption and i...
Stephen Kou, Jens Palsberg
TC
2010
13 years 4 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
12 years 3 days ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...