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» Temporal Extensions to Defeasible Logic
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SACMAT
2009
ACM
14 years 1 months ago
Towards formal security analysis of GTRBAC using timed automata
An access control system is often viewed as a state transition system. Given a set of access control policies, a general safety requirement in such a system is to determine whethe...
Samrat Mondal, Shamik Sural, Vijayalakshmi Atluri
ICALP
2009
Springer
14 years 7 months ago
LTL Path Checking Is Efficiently Parallelizable
We present an AC1 (logDCFL) algorithm for checking LTL formulas over finite paths, thus establishing that the problem can be efficiently parallelized. Our construction provides a f...
Lars Kuhtz, Bernd Finkbeiner
CONCUR
2007
Springer
14 years 1 months ago
Pushdown Module Checking with Imperfect Information
The model checking problem for finite-state open systems (module checking) has been extensively studied in the literature, both in the context of environments with perfect and imp...
Benjamin Aminof, Aniello Murano, Moshe Y. Vardi
CIMCA
2006
IEEE
14 years 1 months ago
Timed-MPSG: A Formal Model for Real-Time Shop Floor Controller
The MPSG (Message-based Part State Graph) model has been developed for the execution portion of shop-floor controllers that operate in a distributed and hierarchical control envir...
Devinder Thapa, Jaeil Park, Gi-Nam Wang, Dongmin S...
CONCUR
1999
Springer
13 years 11 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea