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» Temporal Logic Verification of Lock-Freedom
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ISORC
2000
IEEE
14 years 1 months ago
Verification of UML-Based Real-Time System Designs by Means of cTLA
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
Günter Graw, Peter Herrmann, Heiko Krumm
IJCSA
2006
95views more  IJCSA 2006»
13 years 9 months ago
Modeling and Formal Verification of DHCP Using SPIN
The Dynamic Host Configuration Protocol (DHCP) is a widely used communication protocol. In this paper, a portion of the protocol is chosen for modeling and verification, namely th...
Syed M. S. Islam, Mohammed H. Sqalli, Sohel Khan
COORDINATION
2009
Springer
14 years 10 months ago
Assume-Guarantee Verification of Concurrent Systems
Process algebras are a set of mathematically rigourous languages with well defined semantics that permit modelling behaviour of concurrent and communicating systems. Verification o...
Liliana D'Errico, Michele Loreti
FMCAD
1998
Springer
14 years 2 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
IJCAI
2003
13 years 11 months ago
Formal Verification of Diagnosability via Symbolic Model Checking
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
Alessandro Cimatti, Charles Pecheur, Roberto Cavad...