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» Temporal Logic Verification of Lock-Freedom
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FUIN
2006
85views more  FUIN 2006»
13 years 9 months ago
Towards Integrated Verification of Timed Transition Models
Abstract. This paper describes an attempt to combine theorem proving and model-checking to formally verify real-time systems in a discrete time setting. The Timed Automata Modeling...
Mark Lawford, Vera Pantelic, Hong Zhang
ASWEC
2006
IEEE
14 years 3 months ago
Formal Verification of the IEEE 802.11i WLAN Security Protocol
With the increased usage of wireless LANs (WLANs), businesses and educational institutions are becoming more concerned about wireless network security. The latest WLAN security pr...
Elankayer Sithirasenan, Saad Zafar, Vallipuram Mut...
ECOWS
2006
Springer
14 years 1 months ago
Formal Modelling and Verification of an Asynchronous Extension of SOAP
Current web services are largely based on a synchronous request-response model that uses the Simple Object Access Protocol SOAP. Next-generation telecommunication networks, on the...
Maurice H. ter Beek, Stefania Gnesi, Franco Mazzan...
IJNSEC
2008
190views more  IJNSEC 2008»
13 years 9 months ago
Probabilistic Analysis and Verification of the ASW Protocol using PRISM
The ASW protocol is one of the prominent optimistic fair exchange protocols that is used for contract signing between two participants, the originator and the responder, with the ...
Salekul Islam, Mohammad Abu Zaid
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 10 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu