1016 search results - page 95 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ICSM
1999
IEEE
14 years 1 months ago
1999
IEEE
Exception-handling constructs provide a mechanism for raising exceptions, and a facility for designating protected code by attaching exception handlers to blocks of code. Despite ...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
EURODAC
1994
IEEE
14 years 1 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
SIGSOFT
2007
ACM
14 years 9 months ago
2007
ACM
This paper presents a specification-based approach for systematic testing of products from a software product line. Our approach uses specifications given as formulas in Alloy, a ...
ICSEA
2009
IEEE
14 years 3 months ago
2009
IEEE
—In this paper, it is shown that synthetic images can be used to test specific use cases of a lane tracking algorithm which has been developed by Audi AG. This was achieved by s...