67 search results - page 4 / 14 » Test Resource Partitioning and Reduced Pin-Count Testing Bas... |
ATS
2002
IEEE
14 years 15 days ago
2002
IEEE
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
DFT
2002
IEEE
14 years 15 days ago
2002
IEEE
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...