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» Test-point insertion: scan paths through functional logic
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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 15 days ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...