69 search results - page 9 / 14 » Testing First-Order Logic Axioms in Program Verification |
SIGSOFT
2007
ACM
14 years 9 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
KBSE
2000
IEEE
14 years 6 days ago
2000
IEEE
c specifications provide a powerful method for the specification of abstract data types in programming languages and software systems. Completeness and ground confluence are fundam...
SIGSOFT
2001
ACM
14 years 9 months ago
2001
ACM
This article explores a dual approach to real-time software development. Models are written in UML, as this is expected to be relatively easy and economic. Then models are automat...
SPIN
2000
Springer
14 years 5 days ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
AAAI
2000
13 years 10 months ago
2000
Just as actions can have indirect effects on the state of the world, so too can sensing actions have indirect effects on an agent's state of knowledge. In this paper, we inve...