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ITC
1994
IEEE
151views Hardware» more  ITC 1994»
14 years 1 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey
ISCAS
2003
IEEE
102views Hardware» more  ISCAS 2003»
14 years 3 months ago
A deterministic dynamic element matching approach to ADC testing
A deterministic dynamic element matching (DEM) approach to ADC testing is introduced and compared with a common random DEM method. With both approaches, a highly non-ideal DAC is ...
Beatriz Olleta, Lance Juffer, Degang Chen, Randall...
IJNSEC
2010
98views more  IJNSEC 2010»
13 years 4 months ago
A Random Bit Generator Using Chaotic Maps
Chaotic systems have many interesting features such as sensitivity on initial condition and system parameter, ergodicity and mixing properties. In this paper, we exploit these int...
Narendra K. Pareek, Vinod Patidar, Krishan K. Sud
SIGSOFT
1998
ACM
14 years 2 months ago
Further Empirical Studies of Test Effectiveness
This paper reports on an empirical evaluation of the fault-detecting ability of two white-box software testing techniques: decision coverage (branch testing) and the all-uses data...
Phyllis G. Frankl, Oleg Iakounenko
ICDT
1999
ACM
72views Database» more  ICDT 1999»
14 years 2 months ago
On the Generation of 2-Dimensional Index Workloads
A large number of database index structures have been proposed over the last two decades, and little consensus has emerged regarding their relative e ectiveness. In order to empir...
Joseph M. Hellerstein, Lisa Hellerstein, George Ko...