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» The Chimaera reconfigurable functional unit
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RSP
1999
IEEE
128views Control Systems» more  RSP 1999»
14 years 5 days ago
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are stil...
Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
IPPS
2006
IEEE
14 years 1 months ago
Dynamic configuration steering for a reconfigurable superscalar processor
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...
Nick A. Mould, Brian F. Veale, Monte P. Tull, John...
DASIP
2010
13 years 2 months ago
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
Christophe Lucarz, Ghislain Roquier, Marco Mattave...
ARC
2008
Springer
155views Hardware» more  ARC 2008»
13 years 10 months ago
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems
As embedded applications are getting more complex, they are also demanding highly diverse computational capabilities. The majority of all previously proposed reconfigurable archite...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
FCCM
2005
IEEE
93views VLSI» more  FCCM 2005»
14 years 1 months ago
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
Zion Kwok, Steven J. E. Wilton