In quantitative verification, system states/transitions have associated costs, and these are used to associate mean-payoff costs with infinite behaviors. In this paper, we propose ...
Rajeev Alur, Aldric Degorre, Oded Maler, Gera Weis...
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome...
We present a SAT-based approach to the task and message allocation problem of distributed real-time systems with hierarchical architectures. In contrast to the heuristic approache...
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
It is well-known that modal satisfiability is PSPACE-complete [Lad77]. However, the complexity may decrease if we restrict the set of propositional operators used. Note that there ...