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GC
2008
Springer
13 years 11 months ago
A Bijection for Eulerian-equivalence Classes of Totally Cyclic Orientations
Gioan showed that the number of cycle reversing classes of totally cyclic orientations of a given graph can be calculated as an evaluation of the corresponding Tutte polynomial. We...
Beifang Chen, Arthur L. B. Yang, Terence Y. J. Zha...
ESA
1998
Springer
175views Algorithms» more  ESA 1998»
14 years 3 months ago
Computing the Edit-Distance between Unrooted Ordered Trees
An ordered tree is a tree in which each node's incident edges are cyclically ordered; think of the tree as being embedded in the plane. Let A and B be two ordered trees. The e...
Philip N. Klein
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
14 years 26 days ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh
DAC
1995
ACM
14 years 2 months ago
New Performance-Driven FPGA Routing Algorithms
—Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions signi...
Michael J. Alexander, Gabriel Robins
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 5 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu