Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...