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» The Design and Performance of a Conflict-Avoiding Cache
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MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
16 years 19 days ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
15 years 11 months ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
DAC
2007
ACM
16 years 7 months ago
The KILL Rule for Multicore
Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore's Law for multicore, ...
Anant Agarwal, Markus Levy
HPDC
2007
IEEE
16 years 10 days ago
Cooperative secondary authorization recycling
As distributed applications such as Grid and enterprise systems scale up and become increasingly complex, their authorization infrastructures—based predominantly on the request-...
Qiang Wei, Matei Ripeanu, Konstantin Beznosov
TKDE
1998
77views more  TKDE 1998»
15 years 5 months ago
Techniques for Update Handling in the Enhanced Client-Server DBMS
—The Client-Server computing paradigm has significantly influenced the way modern Database Management Systems are designed and built. In such systems, clients maintain data pages...
Alex Delis, Nick Roussopoulos