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» The Design of Evolutionary Process Modeling Languages
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PADS
2003
ACM
14 years 26 days ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
POPL
2008
ACM
14 years 8 months ago
Multiparty asynchronous session types
Communication is becoming one of the central elements in software development. As a potential typed foundation for structured communication-centred programming, session types have...
Kohei Honda, Nobuko Yoshida, Marco Carbone
CASES
2006
ACM
14 years 1 months ago
Extensible control architectures
Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true ...
Greg Hoover, Forrest Brewer, Timothy Sherwood
UML
2000
Springer
13 years 11 months ago
On the Extension of UML with Use Case Maps Concepts
Descriptions of reactive systems focus heavily on behavioral aspects, often in terms of scenarios. To cope with the increasing complexity of services provided by these systems, beh...
Daniel Amyot, Gunter Mussbacher
MODELS
2007
Springer
14 years 1 months ago
Statechart Development Beyond WYSIWYG
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, have become standard practice in the design of reactive embedded devices. Statecharts are often mor...
Steffen Prochnow, Reinhard von Hanxleden