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HPCA
2003
IEEE
14 years 10 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
HPCA
2002
IEEE
14 years 10 months ago
Modeling Value Speculation
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
Yiannakis Sazeides
HPCA
2001
IEEE
14 years 10 months ago
Reevaluating Online Superpage Promotion with Hardware Support
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. ...
HPCA
2001
IEEE
14 years 10 months ago
A Delay Model and Speculative Architecture for Pipelined Routers
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
Li-Shiuan Peh, William J. Dally
PERCOM
2007
ACM
14 years 9 months ago
Energy-Efficient Data Dissemination for Wireless Sensor Networks
In order to disseminate a large amount of data through a sensor network, it is common to split the data into smallsized chunk packets. If the data is additionally encoded by a for...
Marcel Busse, Thomas Haenselmann, Wolfgang Effelsb...