With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. ...
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
In order to disseminate a large amount of data through a sensor network, it is common to split the data into smallsized chunk packets. If the data is additionally encoded by a for...
Marcel Busse, Thomas Haenselmann, Wolfgang Effelsb...