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CASES
2009
ACM
13 years 10 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
ISPASS
2007
IEEE
14 years 1 months ago
Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance
The ongoing trend of increasing computer hardware and software complexity has resulted in the increase in complexity and overheads of cycle-accurate processor system simulation, e...
Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer...
HIPC
2000
Springer
13 years 11 months ago
Improving Offset Assignment on Embedded Processors Using Transformations
Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas suc...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
PRESENCE
2000
145views more  PRESENCE 2000»
13 years 7 months ago
Control Design and Task Performance in Endoscopic Tele-Operation
Endoscopic surgery, while offering considerable gains for the patient, has created new difficulties for the surgeon. One problem is the fulcrum effect, which causes the movement o...
Ori Ben-Porat, Moshe Shoham, Joachim Meyer
ICIP
2004
IEEE
14 years 9 months ago
A novel compressed domain shot segmentation algorithm on H.264/AVC
This paper presents a novel shot segmentation algorithm on the H.264/AVC video, which operates in the compressed domain. First, the algorithm exploits the intra prediction mode hi...
Yang Liu, Weiqiang Wang, Wen Gao, Wei Zeng