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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
EUROGRAPHICS
2010
Eurographics
14 years 3 months ago
Articulated Billboards for Video-based Rendering
We present a novel representation and rendering method for free-viewpoint video of human characters based on multiple input video streams. The basic idea is to approximate the art...
Marcel Germann, Alexander Hornung, Richard Keiser,...
SI3D
2010
ACM
14 years 2 months ago
Fast capacity constrained Voronoi tessellation
Lloyd relaxation is widely employed to generate point distribution for a variety of applications in computer graphics, computer vision, and image processing. However, Lloyd relaxa...
Hongwei Li, Diego Nehab, Li-Yi Weiy, Pedro V. Sand...
SAC
2009
ACM
14 years 2 months ago
GTfold: a scalable multicore code for RNA secondary structure prediction
The prediction of the correct secondary structures of large RNAs is one of the unsolved challenges of computational molecular biology. Among the major obstacles is the fact that a...
Amrita Mathuriya, David A. Bader, Christine E. Hei...
SC
2009
ACM
14 years 2 months ago
FACT: fast communication trace collection for parallel applications through program slicing
A proper understanding of communication patterns of parallel applications is important to optimize application performance and design better communication subsystems. Communicatio...
Jidong Zhai, Tianwei Sheng, Jiangzhou He, Wenguang...