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CASES
2008
ACM
13 years 8 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
TCAD
2008
101views more  TCAD 2008»
13 years 6 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
IEEEPACT
1998
IEEE
13 years 11 months ago
Static Methods in Hybrid Branch Prediction
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
Dirk Grunwald, Donald C. Lindsay, Benjamin G. Zorn
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 3 days ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
PLDI
2010
ACM
13 years 11 months ago
Finding low-utility data structures
Many opportunities for easy, big-win, program optimizations are missed by compilers. This is especially true in highly layered Java applications. Often at the heart of these misse...
Guoqing Xu, Nick Mitchell, Matthew Arnold, Atanas ...