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TJS
2008
95views more  TJS 2008»
13 years 8 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
EGITALY
2006
13 years 10 months ago
SVG Vectorization by Statistical Region Merging
In this paper a novel algorithm for raster to vector conversion is presented. The technique is mainly devoted to vectorize digital picture maintaining an high degree of photoreali...
Sebastiano Battiato, Giovanni Maria Farinella, Gio...
ITCC
2005
IEEE
14 years 2 months ago
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography
1 Table lookups are one of the most frequently-used operations in symmetric-key ciphers. Particularly in the newer algorithms such as the Advanced Encryption Standard (AES), we fr...
A. Murat Fiskiran, Ruby B. Lee
IJNSEC
2007
137views more  IJNSEC 2007»
13 years 8 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
LCPC
2004
Springer
14 years 2 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...