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ICPP
1999
IEEE
13 years 11 months ago
SLC: Symbolic Scheduling for Executing Parameterized Task Graphs on Multiprocessors
Task graph scheduling has been found effective in performance prediction and optimization of parallel applications. A number of static scheduling algorithms have been proposed for...
Michel Cosnard, Emmanuel Jeannot, Tao Yang
IPPS
2006
IEEE
14 years 1 months ago
Detecting phases in parallel applications on shared memory architectures
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...
Erez Perelman, Marzia Polito, Jean-Yves Bouguet, J...
SIGPLAN
2008
13 years 7 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 8 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
IWMM
2009
Springer
127views Hardware» more  IWMM 2009»
14 years 2 months ago
Investigating the effects of using different nursery sizing policies on performance
In this paper, we investigate the effects of using three different nursery sizing policies on overall and garbage collection performances. As part of our investigation, we modify ...
Xiaohua Guan, Witawas Srisa-an, ChengHuan Jia