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» The Garp Architecture and C Compiler
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IEEEPACT
2000
IEEE
14 years 2 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
IFIPPACT
1994
13 years 11 months ago
Exploiting the Parallelism Exposed by Partial Evaluation
: We describe an approach to parallel compilation that seeks to harness the vast amount of ne-grain parallelism that is exposed through partial evaluation of numerically-intensive ...
Rajeev J. Surati, Andrew A. Berlin
IEEEINTERACT
2003
IEEE
14 years 3 months ago
Procedure Cloning and Integration for Converting Parallelism from Coarse to Fine Grain
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
Won So, Alexander G. Dean
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 4 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
CASES
2006
ACM
14 years 3 months ago
Syntax-driven implementation of software programming language control constructs and expressions on FPGAs
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...
Neil C. Audsley, Michael Ward