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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 2 months ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi
IPPS
2005
IEEE
14 years 2 months ago
A High-Performance Framework for Sun-to-Earth Space Weather Modeling
The Space Weather Modeling Framework (SWMF) aims at providing software architecture for integrated modeling of different domains of Sun-Earth system and high-performance physics-b...
Ovsei Volberg, Tamas I. Gombosi, Kenneth G. Powell...
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 1 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
ICC
2007
IEEE
132views Communications» more  ICC 2007»
14 years 22 days ago
Supporting Bulk Data Transfers of High-End Applications with Guaranteed Completion Time
In high-end grid networks, distributed resources (scientific instruments, CPUs, storages, etc.) are interconnected to support computing-intensive and data-intensive applications, w...
Bin Bin Chen, Pascale Vicat-Blanc Primet
CW
2008
IEEE
14 years 3 months ago
Real-Time Marker Level Set on GPU
Level set methods have been extensively used to track the dynamical interfaces between different materials for physically based simulation, geometry modeling, oceanic modeling and...
Xing Mei, Philippe Decaudin, Bao-Gang Hu, Xiaopeng...