2424 search results - page 216 / 485 » The High Level Architecture for Simulations |
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CASES
2006
ACM
16 years 4 days ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
146
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ISLPED
2009
ACM
16 years 20 days ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
145
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ICASSP
2008
IEEE
16 years 18 days ago
2008
IEEE
Previous studies have shown that wireless DSP algorithms exhibit high levels of data level parallelism (DLP). Commercial and research work in the field of software defined radio...
182
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NOSSDAV
2004
Springer
15 years 11 months ago
2004
Springer
We are developing a distributed architecture for massivelymultiplayer games. In this paper, we focus on designing a low-latency event ordering protocol, called NEO, for this archi...
146
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TCAD
2008
15 years 6 months ago
2008
The verification of a system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, ...