Sciweavers

2424 search results - page 56 / 485
» The High Level Architecture for Simulations
Sort
View
SI3D
1995
ACM
14 years 8 days ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
14 years 10 days ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
CF
2007
ACM
14 years 21 days ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
14 years 2 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
ISCA
2002
IEEE
141views Hardware» more  ISCA 2002»
13 years 8 months ago
SADL: Simulation Architecture Description Language
This paper introduces the Simulation Architecture Description Language (SADL) developed at the National Aeronautics and Space Administration's Marshall Space Flight Center to...
Kenneth G. Ricks, John M. Weirs, B. Earl Wells