Sciweavers

2424 search results - page 7 / 485
» The High Level Architecture for Simulations
Sort
View
SAMOS
2004
Springer
14 years 1 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
WSC
1997
13 years 10 months ago
Simulation of Bulk Flow and High Speed Operations
Simulation modeling can be highly effective for solving problems found in the food, beverage, consumer products, and pharmaceutical industries. The flow of material or fluid in th...
Andrew J. Siprelle, Richard A. Phelps
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
14 years 4 days ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
ISCAPDCS
2007
13 years 10 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
DAC
1997
ACM
14 years 23 days ago
High-Level Power Modeling, Estimation, and Optimization
Enrico Macii, Massoud Pedram, Fabio Somenzi