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WCNC
2010
IEEE
13 years 11 months ago
Impact of Power Control on Relay Load Balancing in Wireless Sensor Networks
—When shortest path routing is employed in large scale multi-hop wireless networks, nodes located near the center of the network have to perform disproportional amount of relayin...
Parth H. Pathak, Rudra Dutta
HPCA
2000
IEEE
13 years 12 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
IEEEPACT
1999
IEEE
13 years 11 months ago
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 17 days ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
ASPLOS
1996
ACM
13 years 11 months ago
The Case for a Single-Chip Multiprocessor
Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we l...
Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ke...